1. Field of the Invention
The present invention relates to a method for manufacturing a silicon carbide semiconductor device, more particularly a method for manufacturing a silicon carbide semiconductor device having a gate electrode.
2. Description of the Background Art
It is known that there is a trade-off generally between the ON resistance and breakdown voltage in a semiconductor device for electric power. In recent years, there has been proposed a semiconductor device having a charge compensation structure such as a super junction structure for the purpose of improving the breakdown voltage while suppressing ON resistance. For example, Japanese Patent Laying-Open No. 2004-342660 discloses a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a charge compensation structure.
According to the art in the aforementioned publication, a p+ type base layer functioning as a channel is folioed on a p-type pillar layer (charge compensation structure). Therefore, the impurities in the charge compensation structure will affect the channel property.